BD3504FVM-TR【PDF 10/19 页】IC REG CTRLR SGL POS ADJ 8MSOP

BD3504FVM,BD3500FVM,BD3501FVM,BD3502FVM

Technical Note

10/16

www.rohm.com

2010.05 - Rev.A

?SPAN class="pst BD3504FVM-TR_2649171_6">Application circuit

Ven

VIN

Vcc

VIN

Ven

Vcc

?SPAN class="pst BD3504FVM-TR_2649171_6">Directions for pattern layout of PCB

鸅ecause a VIN input capacitor causes impedance to drop, mount it as close to the VIN terminal as possible and use thick

wiring patterns. In the event that it causes the wire to come in contact with the inner-layer ground plane, use a plurality of

through holes.

鸅ecause the NRCS terminal is analog I/O, take care to noise. In particular, high-frequency noise of GND may cause IC

maloperation through capacitors. It is recommended to connect GND of NRCS capacitor to IC GND terminal at one

point.

鸗he VFB terminal is an output voltage sense line. Effects of wiring impedance can be ignored by sensing the output

voltage from the load side, but increased sense wiring causes VFB to be susceptible to noise, to which care must be

taken.

鸅ecause the GND terminal is GND to be used in analog circuit inside BD3501/02/04FVM, connect it at one point to

inner-layer GND of substrate by as short pattern as possible. Arrange a bypass capacitor across VCC and GND as close

as possible so that a loop can be minimized.

鸗he G terminal is a terminal for gate drive. If long wiring is inevitable, increase the pattern width and lower impedance.

鸋eat generated in the output transistor can be calculated by:

(VIN - VOUT) ?Io(Max)

Design heat generation not to exceed the guarantee temperature of transistor.

鸆onnect the output capacitor with thick short wiring so that the impedance is lowered. Connect capacitor GND to

inner-layer GND plane by a plurality of through holes.

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